The Peripheral Component Interconnect (hereafter referred to as "PCI") bus is a well-known parallel bus. See "PCI System Architecture" by Tom Shanley and Don Anderson, Mindshare Press, Richardson, Tex. (1993), for general background information on the PCI bus. The subject matter of this document is incorporated herein by reference.
FIG. 1 (Prior Art) is a simplified diagram showing a device 1 including a master 2 which communicates with a target 3 via a PCI bus 4. The PCI bus 4 comprises numerous lines including a clock line PCLK, a frame line FRAME#, time multiplexed address/data lines AD, a parity line PAR, and a data parity error line PERR#. A name followed by a pound symbol (#) indicates that a signal on the line is asserted low.
FIG. 2 (Prior Art) is a waveform diagram of a PCI bus cycle illustrating master 2 writing data into target 3. First the master 2 indicates the beginning of a bus cycle by forcing the FRAME# line low. The master 2 also places the desired address onto the AD lines. The target 3 uses the rising edge 5 of the clock signal PCLK to latch the address on the AD lines into the target. After determining the parity of the address which was placed on the AD lines, the master 2 drives the parity line PAR to the appropriate level. The target 3 uses the next rising edge 6 of the clock signal PCLK to latch the value of the PAR line into the target. The target 3 determines from the address actually received what parity value should have been sent by the master 2 and compares this value with the parity value which was actually received from the master.
Next the master 2 places the data to be written into the target 3 onto the AD lines. The target 3 then uses the next rising edge 7 of the clock signal PCLK to latch the data into the target. The master then drives the parity line PAR with the parity value of the data sent. By latching the parity value sent by the master on the next rising edge 8 and by determining the parity value for the data actually received, the target 3 is able to compare the two parity values as a check for data integrity. If, for example, the parity value determined by the target and received by the target were to disagree, then the target 3 sets the parity error detected bit (bit 15) of a status register 9 of the configuration registers of the target. The target would also drive the parity error response line PERR# low to indicate occurrence of the error to the master. When the master detects the assertion of the parity error response line PERR#, the master logs the error by setting the data parity reported bit (bit 8) of a status register 10 of the configuration registers in the master. The configuration registers are specified by the PCI bus specification.
To test the functioning of PCI bus 4, a special PCI test card 11 is plugged into a spare PCI bus connector slot 12 of device 1. PCI test card 11 can then create an error on the bus. For example, the signal on the parity line PAR can be overridden by the PCI test card so that the value of the parity line PAR as received by the target 3 is incorrect for the data received on the AD lines. Accordingly, the target 3 will detect the parity error, set bit 15 of its status configuration register, and assert the PERR# line low. When the master detects the PERR# line asserted low, the master logs the error by setting bit 8 of the master's status configuration register. Accordingly, the PCI test card 11 is able to generate bus errors on the PCI bus and exercise the error reporting features of the bus to check that the error reporting features of the bus operate as expected.
Testing a device by plugging such a PCI test card into a spare PCI bus slot is, however, generally expensive and requires support and maintenance of the PCI test card. Moreover, a spare PCI bus slot may not be available. Another way of testing the error detecting and reporting capabilities of the PCI bus is therefore sought.